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efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 1/46 4 mbit (512k x 8) 3v only cmos flash memory 1. features ! single supply voltage 2.7v-3.6v ! fast access time: 70/90 ns ! compatible with jedec standard - pinout, packages and software commands compatible with single-power supply flash ! low power consumption - 20ma typical active current - 0.2ua typical standby current ? ! 10,000 minimum program/erase cycles ? ! command register architecture - byte programming (9us typical) - sector erase(sector stru cture: one 16 kb, two 8 kb, one 32 kb, and seven 64 kb) ? ! auto erase (chip & sector) and auto program - any combination of sectors can be erased concurrently; chip erase also provided. - automatically program and verify data at specified address ! erase suspend/erase resume - suspend or resume erasing sectors to allow the read/program in another sector ! ready/busy (ry/ by ) - ry/ by output pin for detection of program or erase operation completion ! end of program or erase detection - data polling - toggle bits ! hardware reset - hardware pin( eset r ) resets the internal state machine to the read mode ! sector protection /unprotection - hardware protect/unprotect any combination of sectors from a program or erase operation. ! low v cc write inhibit is equal to or less than 2.0v ! boot sector architecture - u = upper boot sector - b = bottom boot sector ! packages available: - 40-pin tsopi - 32-pin plcc 2. ordering information part no boot speed package part no boot speed package F49L004UA-70t upper 70 ns tsopi F49L004UA-90 t upper 90 ns tsopi F49L004UA-70n upper 70 ns plcc F49L004UA-90n upper 90 ns plcc f49l004ba-70t bottom 70 ns tsopi f49l004ba-90t bottom 90 ns tsopi f49l004ba-70n bottom 70 ns plcc f49l004ba-90n bottom 90 ns plcc 3. general description the F49L004UA/ f49l004ba is a 4 megabit, 3v only cmos flash memory device organized as 512k bytes of 8 bits. this device is packaged in standard 40-pin tsop and 32-pin plcc. it is designed to be programmed and erased both in system and can in standard eprom programmers. with access times of 70 ns and 90 ns, the F49L004UA/ f49l004ba allows the operation of high-speed microprocessors. the device has separate chip enable ce , write enable we , and output enable oe controls. efst's memory devices reliably store memory data even after 100,000 program and erase cycles. the F49L004UA/ f49l004ba is entirely pin and command set compatible with the jedec standard for 4 megabit flash memory devices. commands are written to the command register using st andard microprocessor write timings. the F49L004UA/ f49l004ba f eatures a sector erase architecture. the device memory array is divided into one 16 kbytes, two 8 kbytes, one 32 kbytes, and seven 64 kbytes. sectors can be erased individually or in groups without affecting the data in other sectors. multiple-sector erase and whole chip erase capabilities provide the flexibility to revise the data in the device. the sector protect/unprotect feature disables both program and erase operations in any combination of the sectors of the memory. this can be achieved in-system or via programming equipment. a low v cc detector inhibits write operations on loss of power. end of program or erase is detected by the ready/busy status pin, data polling of dq7, or by the toggle bit i feature on dq6. once the program or erase cycle has been successfully completed, the device internally resets to the read mode.
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 2/46 4. pin configurations 4.1 40-pin tsop i 4.2 32-pin plcc 4.3 pin description symbol pin name functions a0~a18 address input to provide memory addresses. dq0~dq7 data input/output to output data when read and receive data when write. the outputs are in tri-state when oe or ce is high. ce chip enable to activate the device when ce is low. oe output enable to gate t he data output buffers. we write enable to control the write operations. reset reset hardware reset pin/sector protect unprotect (for 40-tsop) ry/ by ready/busy to check device o peration status(for 40 tsop) v cc power supply to provide power gnd ground 5 6 7 8 9 10 11 12 13 a7 a6 a5 a4 a3 a2 a1 a0 dq0 29 28 27 26 25 24 23 22 21 a14 a13 a8 a9 a11 oe a10 ce dq7 dq6 dq5 dq4 dq3 gnd dq2 dq1 32 31 30 a17 we v cc a18 a16 a15 a12 14 15 16 17 18 19 20 4 3 2 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 a16 a15 a14 a13 a12 a11 a9 a8 we reset nc ry /b y a18 a7 a6 a5 a4 a3 a2 a1 a17 vss nc nc a10 dq7 dq6 dq5 dq4 vcc vcc nc dq3 dq2 dq1 dq0 oe vss ce a0
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 3/46 5. sector structure table 1: F49L004UA sector address table sector address sector sector size (kbytes) address range a18 a17 a16 a15 a14 a13 sa10 16 7c000h-7ffffh 11111x sa9 8 7a000h-7bfffh 111101 sa8 8 78000h-79fffh 111100 sa7 32 70000h-77fffh 1110xx sa6 64 60000h-6ffffh 1 1 0 x x x sa5 64 50000h-5ffffh 1 0 1 x x x sa4 64 40000h-4ffffh 1 0 0 x x x sa3 64 30000h-3ffffh 0 1 1 x x x sa2 64 20000h-2ffffh 0 1 0 x x x sa1 64 10000h-1ffffh 0 0 1 x x x sa0 64 00000h-0ffffh 0 0 0 x x x table 2: f49l004ba sector address table sector address sector sector size (kbytes) address range a18 a17 a16 a15 a14 a13 sa10 64 70000h-7ffffh 1 1 1 x x x sa9 64 60000h-6ffffh 1 1 0 x x x sa8 64 50000h-5ffffh 1 0 1 x x x sa7 64 40000h-4ffffh 1 0 0 x x x sa6 64 30000h-3ffffh 0 1 1 x x x sa5 64 20000h-2ffffh 0 1 0 x x x sa4 64 10000h-1ffffh 0 0 1 x x x sa3 32 08000h-0ffffh 0001xx sa2 8 06000h-07fffh 000011 sa1 8 04000h-05fffh 000010 sa0 16 00000h-03fffh 00000x
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 4/46 6. functional block diagram control input logic sense amplifier pgm data hv program data latch write state maching (wsm) state register command data decoder command data latch address latch and buff er a0~a18 ce oe we reset (for40-tsop) program / erase high voltage f49l004u(b)a flash array y-decoder x-decoder y-pass gate i / o buffer dq0~dq7 array source hv
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 5/46 7. functional description 7.1 device operation this section describes the requirements and use of the device bus operati ons, which are initiated through the internal command register. the register is composed of latches that store the command, address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state mach ine outputs dictate the function of the device. the F49L004UA/ f49l004ba features various bus operations as table 3. table 3. F49L004UA/f49l004ba operation modes selection address description ce oe we reset a18 | a13 a12 | a10 a9 a8 | a7 a6 a5 | a2 a1 a0 dq0~dq7 reset(3) x x x l, vss 0.3v(4) x high z read l l h h ain dout write l h l h ain din output disable l h h h x high z standby v cc 0.3v xx v cc 0.3v x high z sector protect(2) l h l v id saxxxlxhl din sector unprotect(2) l h l v id saxxxhxhl din temporary sector unprotect x x x v id ain din auto-select see table 4 notes: 1. l= logic low = v il , h= logic high = v ih , x= don't care, sa= sector address, v id =11.5v to 12.5v. ain= address in, din = da ta in, dout = data out. 2. the sector protect and unprotec t functions may also be implemented via programming equipment. 3. eset r pin for 40-tsop package type only. 4. see ?reset mode? section.
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 6/46 table 4. F49L004UA/f49l004ba auto-select mode (high voltage method) address dq0~dq7 description ce oe we reset a18 | a13 a12 | a10 a9 a8 | a4 a3 a2 a1 a0 llh h x xv id xlhll 7fh llh h x xv id xhl l l 7fh llh h x xv id xhhl l 7fh (manufacturer id:efst) llh h x xv id xllll 8ch (device id: F49L004UA) l l h h x x v id xxxlh b5h (device id: f49l004ba) l l h h x x v id xxxlh b6h sector protection verify l l h h sa x v id x x x h x code(2) notes : 1.manufacturer and device codes may also be accessed via the software command sequence in table 5. 2. code=00h means unprotected. code =01h means protected.
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 7/46 reset mode : hardware reset (for 40-tsop package ) when the eset r pin is driven low for at least a period of t rp , the device immediately te rminates any operation in progress, tri-states all output pins, and ignores all read/write commands for the duration of the eset r pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated later once the device is ready to accept another command sequence, to ensure the data integrity. the current is reduced for the duration of the eset r pulse. when eset r is held at v ss 0.3v, the device draws cmos standby current (i cc4 ). if eset r is held at v il but not within v ss 0.3v, the standby current will be greater. the eset r pin may be tied to system reset circuitry. a system reset would thus reset the flash memory, enabling the system to r ead the boot-up firm-ware from the flash memory. if eset r is asserted during a program or erase embedded algorithm operation, the ry/ by pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of t ready (during embedded algorithms). the system can thus monitor ry/ by to determine whether the reset operation is complete. if eset r is asserted when a program or erase operation is not executing , i.e. the ry/ by is ?1?, the reset operation is completed within a time of t ready (not during embedded algorithms). the system can read data after t rh when the eset r pin returns to v ih . refer to the ac characteristics tables for hardware reset section. read mode to read array data from the outputs, the system must drive the ce and oe pins to v il . ce is the power control and selects the device. oe is the output control and gates array data to the output pins. we should remain at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor?s read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see ?read command? section for more information. refer to the ac read operations t able for timing specifications and to figure 5 for the timing diagram. i cc1 in the dc characteristics table repr esents the active current specification for reading array data. write mode to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), t he system must drive we and ce to v il , and oe to v ih . the ?program command? section has details on programming data to the device using standard command sequences. an erase operation can erase one sector, multiple sectors, or the entire device. tables 1 and 2 indicate the address space that each sector occupies. a ?sector address? consists of the address bits required to uniquely select a sector. the ?software command definitions? section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. when the system writes the auto-select command sequence, the device enters the auto-select mode. the system can then read auto-sele ct codes from the internal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the auto-select mode and auto-select command sections for more information. i cc2 in the dc characteristics table repr esents the active current specification for the write m ode. the ?ac characteristics? section contains timing specification tables and timing diagrams for write operations. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the device automatically enables this mode when addresses remain unchanged for over 250ns ns. the automatic sleep mode is independent of the ce , we , and oe control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. i cc4 in the dc characteristics table represents the autom atic sleep mode current specification.
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 8/46 temporary sector unprotect mode this feature allows temporar y unprotection of previously protected sector to change data in-system. this mode is activated by setting the eset r pin to v id (11.5v-12.5v). during this mode, all formerly protected sectors are un- protected and can be programm ed or erased by selecting the sector addresses. once v id is removed from the eset r pin, all the previously protected sectors are protected again. notes: 1. all protected sectors unprotected. 2. all previously protected se ctors are protected once again. start reset = v id (note 1) perform erase or program operations reset = v ih temporary sector unprotect completed (note 2)
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 9/46 output disable mode with the oe is at a logic high level (v ih ), outputs from the devices are disabled. this will cause the output pins in a high impedance state standby mode when ce and eset r are both held at v cc 0.3v, the device enter cmos standby mode. if ce and eset r are held at v ih , but not within the range of v cc 0.3v, the device will still be in the standby mode, but the standby current will be larger. if the device is deselected during auto algorithm of erasure or programming, the device draws active current i cc2 until the operation is completed. i cc3 in the dc characteristics table represents the standby current specification. the device requires standard access time (t ce ) for read access from either of thes e standby modes, before it is ready to read data. sector protect / un-protect mode the hardware sector protec t feature disables both program and erase operations in any sector. the hardware sector unprotect feature re-enables both the program and erase operations in previously protected sectors. sector protect/ unprotect can be implemented via two methods. the primary method requires v id on the eset r pin only, and can be implemented either in-system or via programming equipment. figure 16 shows the algorithms and figure 15 shows the timing diagram. this method uses standard microprocessor bus cycle timing. for sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. the alternate method intended only for programming equipment requires v id on address pin a9, oe , and eset r . auto-select mode the auto-select mode provides manufacturer and device identification and sector protection verification, through outputs on dq7?dq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the auto-select codes can also be accessed in-system through the command register. when using programming equipment, this mode requires v id (11.5 v to 12.5 v) on address pin a9. while address pins a3, a2, a1, and a0 must be as shown in table 4. to verify sector protection, all necessary pins have to be set as required in table 4, the programming equipment may then read the corresponding identifier code on dq7-dq0. to access the auto-select codes in-system, the host system can issue the auto-select command via the command register, as shown in table 5. this method does not require v id . see ? software command definitions? for details on using the auto-select mode. 7.2 software command definitions writing specific address and data commands or sequences into the command register initiates the device operations. table 5 def ines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. all addresses are latched on the falling edge of we or ce , whichever happens later. all data is latched on the rising edge of we or ce , whichever happens first. refer to the correspon ding timing diagrams in the ac characteristics section.
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 10/46 table 5. F49L004UA/ f49l004ba software command definitions 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle command bus cycles addr data addr data addr data addr data addr data addr data reset (5) 1xxxhf0h---------- read (4) 1 ra rd ---------- program 4 555h aah 2aah 55h 555h a0h pa pd chip erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h sector erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h sector erase suspend (6) 1xxxhb0h---------- sector erase resume (7) 1xxxh30h---------- auto-select see table 6. notes: 1. x = don?t care ra = address of memory location to be read. rd = data to be read at location ra. pa = address of memory location to be programmed. pd = data to be programmed at location pa. sa = address of the sector. 2. except read command and auto-select command, all command bus cycles are write operations. 3. address bits a18?a11 are don?t cares. 4. no command cycles required when reading array data. 5. the reset command is required to return to reading array data when device is in the auto-select mode, or if dq5 goes high(while the device is providing status data). 6. the system may read and program in non-erasing sect ors, or enter the auto-select mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 7. the erase resume command is valid only during the erase suspend mode. table 6. F49L004UA/ f49l004ba auto-select command 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle command bus cycles addr data addr data addr data addr data addr data addr data 4 555h aah 2aah 55h 555h 90h x04h 7fh - - - - 4 555h aah 2aah 55h 555h 90h x08h 7fh - - - - 4 555h aah 2aah 55h 555h 90h x0ch 7fh - - - - manufacture id 4 555h aah 2aah 55h 555h 90h x00h 8ch - - - - device id, upper boot 4 555h aah 2aah 55h 555h 90h x01h b5h - - - - device id, bottom boot 4 555h aah 2aah 55h 555h 90h x01h b6h - - - - sector protect verify 4 555h aah 2aah 55h 555h 90h (sa) x02h 00h 01h ---- notes : 1. the fourth cycle of the auto-se lect command sequence is a read cycle. 2. for sector protect verify operatio n: if read out data is 01h, it means t he sector has been protected. if read out data is 00h, it means the sect or is still not being protected.
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 11/46 reset command writing the reset command to the device resets the device to reading array data. address bits are all don?t cares for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to reading array data (also applies to programming in erase suspend mode). once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an auto-select command sequence. once in the auto-select mode, the reset command must be written to return to reading array data (also applies to auto-select during erase suspend). if dq5 goes high(see ?dq5: exceeded timing limits? section) during a program or erase operation, writing the reset command returns the device to reading array data (also applies during erase suspend). read command the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. when the device accepts an erase suspend command, the device enters the er ase suspend mode. the system can read array data using the standard read timings, except that if it reads an address within erase- suspended sectors, the dev ice outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see ?erase suspend/erase resume commands? for more information on this mode. the system must issue the reset command to re-enable the device for reading array data if dq5 goes high, or while in the auto-select mode. see the ?reset command? section. see also the ?read mode? in the ?device operations? section for more info rmation. refer to figure 5 for the timing diagram. program command the program command sequence programs one byte into the device. programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically provid es internally generated program pulses and verifies the programmed cell margin. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. the system can determine the status of the program operation by using dq7, dq6, or ry/ by . see ?write operation status? section for more information on these status bits. any commands written to the device during the embedded program algorithm ar e ignored. note that a hardware reset immediately terminates the programming operation. the program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a ?0? back to a ?1?. attempti ng to do so may halt the operation and set dq5 to ?1?, or cause the data polling algorithm to indicate the operation was successful. however, a succeeding read will show that the data is still ?0?. only erase operations can convert a ?0? to a ?1?. chip erase command chip erase is a six-bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. any commands written to the chip during the embedded erase algorithm ar e ignored. note that a hardware reset during the chip erase operation immediately terminates the o peration. the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure the data integrity.
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 12/46 the system can determine t he status of the erase operation by using dq7, dq6, dq2, or ry/ by . see ?write operation status? section for more information on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. see the erase/program operations tables in ?ac characteristics? for parameters. sector erase command sector erase is a six-bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the address of the sector to be er ased, and the sector erase command. the device does not require the system to preprogram the memory prior to erase. the embedded erase algorithm automatically programs and veri fies the sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of 50 s begins. during the time-out period, additional sector addresses and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. if the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor dq3. any command other than sector erase or erase suspend during the time-out period resets the device to reading array data. the sy stem must rewrite the command sequence and any additional sector addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out. (see the ?dq3: sector erase timer? section.) the time-out begins from the rising edge of the final we pulse in the command sequence. once the sector erase oper ation has begun, only the erase suspend command is valid. all other commands are ignored. note that a hardware reset during the sector erase operation immediately terminates the operation. the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure the data integrity. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the syst em can determine the status of the erase operation by using dq7, dq 6, dq2, or ry/ by . (refer to ?write operation status? section for more informati on on these status bits.) refer to the erase/program operations tables in the ?ac characteristics? section for parameters. sector erase suspend/resume command the erase suspend command allows the system to interrupt a sector erase o peration and then read data from, or program data to, any sector not selected for erasure (the device ?erase suspends? all sectors selected for erasure.). this command is valid only during the sector erase oper ation, including the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. addresses are ?don?t-cares? when writing the erase suspend command as shown in table 5. when the erase suspend command is written during a sector erase operation, t he device requires a maximum of 20 s to suspend the erase operation. however, when the erase suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. reading at any address within erase-suspended sectors produces stat us data on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is ac tively erasing or is erase- suspended. see ?write oper ation status? section for more informati on on these status bits. after an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see ?write operation status? for more information. the system may also writ e the auto-select command sequence when the device is in the erase suspend mode. the device allows reading auto-select codes even at addresses within er asing sectors, since the codes are not stored in the memory array. when the device exits the auto-select mode, the device reverts to the erase suspend mode, and is ready for another valid operation.
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 13/46 the system must write the erase resume command (address bits are ?don?t care? as shown in table 5) to exit the erase suspend mo de and continue the sector erase operation. further writes of the resume command are ignored. another erase suspend command can be written after the device has resumed erasing. auto-select command the auto-select command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. table 6 shows the address and data requirements. this method is an alternative to t hat shown in table 4, which is intended for prom programmers and requires v id on address bit a9. the auto-select command sequence is initiated by writing two unlock cycles, followed by the auto-select command. the device then enters the auto-select mode, and the system may read at any address any number of times, without initiating another command sequence. the read cycles at address 04h, 08h, 0ch, and 00h retrieves the efst manufacturer id. a read cycle at address 01h retrieves the device id. a read cycle containing a sector a ddress (sa) and the address 02h returns 01h if that sector is protected, or 00h if it is unprotected. refer to tables 1 and 2 for valid sector addresses. the system must write the reset command to exit the auto-select mode and return to reading array data. 7.3 write operation status the device provides several bits to determine the status of a write operation: ry/ by , dq7, dq6, dq5, dq3, dq2, and. table 7 and the following subsections describe the functions of these bits. ry/ by , dq7, and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. table 7. write operation status status dq7 (note1) dq6 dq5 (note2) dq3 dq2 ry/ by embedded program algorithm 7 dq toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 reading erase suspended sector 1 no toggle 0 n/a toggle 1 reading non-erase suspended sector data data data data data 1 in progress erase suspended mode erase suspend program 7 dq toggle 0 n/a n/a 0 embedded program algorithm 7 dq toggle 1 n/a no toggle 0 embedded erase algorithm 0 toggle 1 1 toggle 0 exceeded time limits erase suspend program 7 dq toggle 1 n/a n/a 0 notes: 1. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 2. dq5 switches to ?1? when an embedded program or embedded erase operation has exceeded the maximum timing limits. see ?dq5: exceeded ti ming limits? for more information.
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 14/46 ry/ by : ready/busy (for 40-pin tsop package) the ry/ by is a dedicated, open-drain output pin that indicates whether an embedded algorithm is in progress or complete. the ry/ by status is valid after the rising edge of the final we pulse in the command sequence. since ry/ by is an open-drain output, several ry/ by pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), t he device is actively erasing or programming. (this includes programming in the erase suspend mode.) if the out put is high (ready), the device is ready to read array data (including during the erase suspend mode), or is in the standby mode. table 7 shows the outputs for ry/ by . dq7: data polling the dq7 indicates to the host system whether an embedded algorithm is in progress or completed, or whether the device is in erase suspend mode. the data polling is valid after the rising edge of the final we pulse in the program or erase command sequence. during the embedded program algorithm, the device outputs on dq7 the comple ment of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the true data on dq7. the system must pr ovide the program address to read valid status info rmation on dq7. if a program address falls within a protected sector, data polling on dq7 is active for approxim ately 1 s, then the device returns to reading array data. during the embedded erase algorithm, data polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all sectors selected for erasing ar e protected, data polling on dq7 is active for approximately 100 s, then the device returns to reading array data. if not all selected sectors are protected, t he embedded erase algorithm erases the unprotected se ctors, and ignores the selected sectors that are protected. when the system detects dq 7 has changed from the complement to true data, it can read valid data at dq7~ dq0 on the following read cycles. this is because dq7 may change asynchronously with dq0?dq6 while output enable ( oe ) is asserted low. refer to figure 21, data polling timings (during embedded algorithms), figure 19 shows the data polling algorithm. dq6:toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cycles to any address cause dq6 to toggle. the system may use either oe or ce to control the read cycles. when the operation is complete, dq6 stops toggling. when an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all selected se ctors are protected, the embedded erase algorithm er ases the unprotected sectors, and ignores the se lected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (i.e. the embedded erase algorithm is in progress), dq6 toggles. when the dev ice enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternatively, the system can use dq7. if a program address falls within a protected sector, dq6 toggles for approximatel y 2 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. table 7 shows the outputs for toggle bit i on dq6. figure 20 shows the toggle bit algorithm. figure 22 shows the toggle bit timing diagrams. figure 25 shows the differences between dq2 and dq6 in graphical form. refer to the subsection on dq2: toggle bit ii. dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we or ce , whichever happens first, in the command sequence.
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 15/46 dq2 toggles when the sy stem reads at addresses within those sectors that have been selected for erasure. (the system may use either oe or ce to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase- suspended. dq6, by comparison, indi cates whether the device is actively erasing, or whethe r is in erase-suspended, but cannot distinguish which sectors are selected for erasure. thus, both status bi ts are required for sector and mode information. refer to table 7 to compare outputs for dq2 and dq6. figure 20 shows the toggle bit algorithm in flowchart form. see also the dq6: t oggle bit i subsection. figure 22 shows the toggle bit timing diagram. figure 25 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/ dq2 refer to figure 20 for the following discussion. whenever the system initiall y begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or er ase operation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bi t is still toggling, the system should note whether the val ue of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopp ed toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is st ill toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described earlier. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded the specified limits(internal pulse count). under these conditions dq5 will produce a "1". this time-out condition indicates that the program or erase cycle was not successfully co mpleted. data polling and toggle bit are the only operat ing functions of the device under this condition. if this time-out condition occurs during sector erase operation, it specifies that a particular sector is bad and it may not be reused. howeve r, other sectors are still functional and may be used for the program or erase operation. the device must be reset to use other sectors. write the reset command sequen ce to the device, and then execute program or erase command sequence. this allows the system to continue to use the other active sectors in the device. if this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad. if this time-out condition occurs during the programming operation, it s pecifies that the sector containing that byte is ba d and this sector may not be reused, however other sectors are still functional and can be reused. the time-out condition will not appear if a user tries to program a non blank location without erasing. please note that this is not a device failure condition since the device was incorrectly used. dq3:sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not an erase operation has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are select ed for erasure, the entire timeout also applies after each additional sector erase command. when the time-out is complete, dq3 switches from ?0? to ?1.? if the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor dq3. when the sector erase command sequence is written, the system should read the status on dq7 (data polling) or dq6 (toggle bit i) to ensure the device has accepted the command sequence, and then read dq3. if dq3 is ?1?, the internally controlled erase cycle has begun; all further commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0?, the device wi ll accept additional sector erase commands. to ensure the command has been accepted, the system softwa re should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. table 7 shows the outputs for dq3.
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 16/46 7.4 more device operations hardware data protection the command sequence requirement of unlock cycles for programming or erasing provid es data protection against inadvertent writes. in addition, the following hardware data protection measures prev ent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than vlko, the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent uni ntentional writes when v cc is greater than v lko . write pulse "glitch" protection noise pulses of less than 5 ns (typical) on oe , ce or we do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe = v il , ce = v ih or we = v ih . to initiate a write cycle, ce and we must be a logical zero while oe is a logical one. power supply decoupling in order to reduce power switching effect, each device should have a 0.1uf ceramic capacitor connected between its v cc and gnd. power-up sequence the device powers up in the read mode. in addition, the memory contents may only be altered after successful completion of the predefined command sequences. power-up write inhibit if we = ce = v il and oe = v ih during power up, the device does not accept commands on the rising edge of we . the internal state machine is automatically reset to reading array data on power-up.
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 17/46 8. absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . ?65 c to +150 c ambient temperature with power applied. . . . . . . .. . . . . . ?65 c to +125 c voltage with respect to ground v cc (note 1) . . . . . . . . . . .?0.5 v to +4.0 v a9 , oe , and eset r (note 2) ?. . . .. . . . . ?0.5 v to +12.5 v all other pins (note 1). . . . . . . . . . ?0.5 v to v cc +0.5 v output short circuit current (note 3) .. . .. 200 ma notes: 1. minimum dc voltage on in put or i/o pins is ?0.5 v. during voltage transit ions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 1. maximum dc voltage on input or i/o pins is v cc +0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 2. 2. minimum dc input voltage on pins a9, oe , and eset r is -0.5 v. during voltage transitions, a9, oe , and eset r may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 1. maximum dc input voltage on pin a9 is +12.5 v which may overshoot to 14.0 v for periods up to 20 ns. 3. no more than one out put may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. figure 1. maximum negative overshoot waveform figure 2. maximum positive overshoot waveform +0.8v -0.5v -2.0v 20ns 20ns 20ns vcc +2.0v vcc +0.5v 2.0v 20ns 20ns 20ns
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 18/46 operating ranges commercial (c) devices ambient temperature (ta) . . . . . . . . . . . 0c to +70c v cc supply voltages v cc for all devices . . . . . . . . . . . . . . . . . . . . .2.7 v to 3.6 v operating ranges define t hose limits between which the functi onality of the device is guaranteed. table 8. capacitance t a = 25c , f = 1.0 mhz symbol description conditions min. typ. max. unit c in1 input capacitance v in = 0v 8 pf c in2 control pin capacitance v in = 0v 12 pf c out output capacitance v out = 0v 12 pf 9. dc characteristics table 9. dc characteristics t a = 0c to 70c, v cc = 2.7v to 3.6v symbol description conditions min. typ. max. unit i li input leakage current v in = v ss or v cc , v cc = v cc max. 1ua i lit a9 input leakage current v cc = v cc max; a9=12.5v 35 ua i lo output leakage current v out = v ss or v cc , v cc = v cc max 1ua @5mhz 712ma i cc1 v cc active read current ce = v il , oe = v ih @1mhz 2 4 ma i cc2 v cc active write current ce = v il , oe = v ih 15 30 ma i cc3 v cc standby current ce ; eset r = v cc 0.3v 0.2 5 ua i cc4 v cc standby current during reset eset r = v ss 0.3v 0.2 5 ua i cc5 automatic sleep mode v ih = v cc 0.3v; v il = v ss 0.3v 0.2 5 ua v il input low voltage(note 1) -0.5 0.8 v v ih input high voltage 0.7x v cc v cc + 0.3 v v id voltage for auto-select and temporary sector unprotect v cc =3.3v 11.5 12.5 v v ol output low voltage i ol = 4.0ma, v cc = v cc min 0.45 v v oh1 output high voltage(ttl) i oh = -2ma, v cc = v cc min 0.85x v cc v oh2 output high voltage i oh = -100ua, v cc min v cc -0.4 v lko low v cc lock-out voltage 2.3 2.5 v notes : 1. v il min. = -1.0v for pulse width is equal to or less than 50 ns. v il min. = -2.0v for pulse width is equal to or less than 20 ns. 2. v ih max. = v cc + 1.5v for pulse width is equal to or less than 20 ns if v ih is over the specified maximum valu e, read operation ca nnot be guaranteed. 3. automatic sleep mode enable the low power mode when addresses remain stable for 250 ns
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 19/46 10. ac characteristics test conditions figure 3. test setup figure 4. input waveforms and measurement levels input 3.0v 0v 1.5v output 1.5v test points ac testing : inputs are driven at 3.0v for a logic "1" and 0v for a logic "0" input pulse rise and fall times are < 5ns. 6.2k diodes = in3064 or equivalent +3.3v 2.7k cl = 100pf including jig capacitance cl = 30pf for f49l004u(b)a cl device under test
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 20/46 10.1 read operation ta = 0c to 70c, v cc = 2.7v~3.6v table 10. read operations -70 -90 symbol description conditions min. max. min. max. unit t rc read cycle time (note 1) 70 90 ns t acc address to output delay ce = oe = v il 70 90 ns t ce ce to output delay oe = v il 70 90 ns t oe oe to output delay ce = v il 30 35 ns t df oe high to output float (note1) ce = v il 25 30 ns t oeh output enable read 00ns hold time toggle and data polling 10 10 ns t oh address to output hold ce = oe = v il 00ns notes : 1. not 100% tested. 2. t df is defined as the time at which the output achiev es the open circuit condition and data is no longer driven. figure 5. read timing waveform t rc addresses stable output valid address high-z ce we 0v ry/by reset oe outputs high-z t acc t oeh t oe t oh t df t ce
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 21/46 10.2 program/erase operation table 11. we controlled program/erase operations(t a = 0c to 70c, v cc = 2.7v~3.6v) -70 -90 symbol description min. max. min. max. unit t wc write cycle time (note 1) 70 90 ns t as address setup time 0 0 ns t ah address hold time 45 45 ns t ds data setup time 35 35 ns t dh data hold time 0 0 ns t oes output enable setup time 0 0 ns t ghwl read recovery time before write ( oe high to we l ow) 00ns t cs ce setup time 00ns t ch ce hold time 00ns t wp write pulse width 35 35 ns t wph write pulse width high 30 30 ns t whwh1 programming operation (note 2) (byte program time) 9(typ.) 9(typ.) us t whwh2 sector erase operation (not e 2) 0.7(typ.) 0.7(typ.) sec t vcs v cc setup time (note 1) 50 50 us t rb recovery time from ry/ by 00ns t busy program/erase valid to ry/ by delay 90 90 ns notes : 1. not 100% tested. 2. see the "erase and programming performance" section for more information.
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 22/46 table 12. ce controlled program/erase operations(t a = 0c to 70c, v cc = 2.7v~3.6v) -70 -90 symbol description min. max. min. max. unit t wc write cycle time (note 1) 70 90 ns t as address setup time 0 0 ns t ah address hold time 45 45 ns t ds data setup time 35 35 ns t dh data hold time 0 0 ns t oes output enable setup time 0 0 ns t ghel read recovery time before write 0 0 ns t ws we setup time 00ns t wh we hold time 00ns t cp ce pulse width 35 35 ns t cph ce pulse width high 30 30 ns t whwh1 programming operation(note2) 9(typ.) 9(typ.) us t whwh2 sector erase operation (n ote2) 0.7(typ.) 0.7(typ.) sec notes : 1. not 100% tested. 2. see the "erase and programming performance" section for more information.
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 23/46 figure 6. write command timing waveform oe data v ih v il add valid v ih v il v ih v il v ih v il v ih v il t ah t as t wp t wph vcc 3v address we ce t cwc t cs t ch t dh t dh din t oes
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 24/46 figure 7. embedded programming timing waveform notes : 1. pa = program address, pd = program data, dout = data out , dq7 = complement of data written to device 2. figure indicates the last two bus cycles of the command sequence.. address we ce oe 555 for program 2aa for erase data polling t as t wc pd data reset ry/by pa for program sa for sector erase 555 for chip erase a0 for p rog ram 55 for erase pd for program 30 for sector erase 10 for chip erase t wh t ah t ds t dh t ghel t cp t cph t busy t ws dout dq7 t whwh1 or 2 t rh
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 25/46 figure 8. embedded programming algorithm flowchart start write data aah address 555h verify work ok? embedded program completed data poll from system yes last address? yes no write data 55h address 2aah write data a0h address 555h no increment address
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 26/46 figure 9. ce controlled program timing waveform notes : 1. pa = program address, pd = program data, dout = data out , dq7 = complement of data written to device 2. figure indicates the last two bus cycles of the command sequence.. address we ce oe 555 for program 2aa for erase data polling t as t wc pd data reset ry/by pa for program sa for sector erase 555 for chip erase a0 for program 55 for erase pd for program 30 for sector erase 10 for chip erase t wh t ah t ds t dh t ghel t cp t cph t busy t ws dout dq7 t whwh1 or 2 t rh
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 27/46 figure 10. embedded chip erase timing waveform notes : sa = sector address (for sector erase, va = valid address for reading status data (see "write operation status") address ce we oe 2aaah 555h va va t wc t as erase command sequence(last two cycle) read status data t ah t ch t ghwl t wp t cs t wph 55h t ds t dh 10h in progress complete t whwh1 data t rb t busy ry/by t vcs vcc
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 28/46 figure 11. embedded chip erase algorithm flowchart start write data aah address 555h embedded chip erease completed data = ffh? yes no write data 55h address 2aah write data 80h address 555h write data aah address 555h write data 55h address 2aah write data 10h address 555h data poll from system
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 29/46 figure 12. embedded sector erase timing waveform notes : sa = sector address (for sector erase, va = valid address for reading status data (see "write operation status") address ce we oe 2aaah sa va va t wc t as erase command sequence(last two cycle) read status data t ah t ch t ghwl t wp t cs t wph 55h t ds t dh 30h in progress complete t whwh1 data t rb t busy ry/b y t vcs vcc
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 30/46 figure 13. embedded sector erase algorithm flowchart start write data aah address 555h embedded sector erease completed last sector to erase yes no write data 55h address 2aah write data 80h address 555h write data aah address 555h write data 55h address 2aah write data 30h address sa data poll from system data = ffh? no
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 31/46 figure 14. erase suspend/erase resume flowchart start write data b0h toggle bit checking q6 not toggled yes erase resume no erase suspend read array or program another erase suspend? no no yes reading or programming end yes write data 30h continue erase
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 32/46 figure 15. in-system sector protect/unprotect timing waveform ( rese t control) notes : when sector protect, a6=0, a1=1. when sector unprotect, a6=1, a1=1, a0=0. ce reset sa,a6 a1,a0 data t wp sector protect sector unprotect valid* valid* valid* 60h 60h 40h status verify we sector protect = 150us sector unprotect = 15ms oe
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 33/46 figure 16. in-system sector protect/unprotect algorithm ( rese t = v id ) start start plscnt = 1 plscnt = 1 set up first sector address sector unprotect : write 60h to sector address with a6 = 1, a1 = 1, a0 = 0 wait 15 ms first write cycle = 60h? all sectors protected? data = 00h? last sector verified? no reset = v id no no yes yes no no no yes yes first write cycle = 60h? temporary sector unprotect mode set up next sector address device failed device failed yes wait 1 s temporary sector unprotect mode data = 01h? yes reset = v id plscnt = 1000? wait 1 s increment plscnt set up sector address sector protect : write 60h to sector address with a6 = 0, a1 = 1, a0 = 0 verify sector protect : write 40h to sector address with a6 = 0, a1 = 1, a0 = 0 wait 150 s read from sector address with a6 = 0, a1 = 1, a0 = 0 plscnt = 25? increment plscnt protect another sector? no no no remove v id from reset remove v id from reset write reset command write reset command sector protect complete sector protect complete sector protect algorithm sector unprotect algorithm yes reset plscnt = 1 protect all sector : the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address yes yes read from sector address with a6 = 1, a1 = 1, a0 =0 verify sector unprotect : write 40h to sector address with a6 = 1, a1 = 1, a0 =0
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 34/46 figure 17. sector protect timing waveform (a9, oe control) oe a0,a1 a6 a9 we 12v 3v ce data a18~a12 12v 3v t vlht t vlht verify t oesp t wpp1 01h f0h t oe t vlht sector address
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 35/46 figure 18. sector protection algorithm (a9, oe control) start set up sector address data = 01h? sector protection complete activate we pluse remove vid from a9 write reset command device failed protect another sector? yes yes no no plscnt = 1 oe = v id , a9 = v id , ce = v il a6 = v il time out 150us set we = v ih , ce = oe = v il a9 should remain v id read from sector address = sa, a0 = 1, a1 = 1 plscnt = 32?
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 36/46 write operation status figure 19. data polling algorithm notes : 1. va =valid address for programming. 2. q7 should be re-checked even q5 = "1" because q7 may change simultaneously with q5. start read q7~q0 add. = va(1) q7 = data? fail pass q5 = 1? no read q7~q0 add. = va yes yes no q7 = data? yes no (2)
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 37/46 figure 20. toggle bit algorithm note : 1. read toggle bit twice to deter mine whether or not it is toggle. 2. recheck toggle bit because it may stop toggling as q5 change to "1". start read q7 ~ q0 toggle bit = q6 toggle? program / erase operation not complete, write reset command program / erase operation complete q5 = 1? no read q7~q0 twice yes no toggle bit q6 = toggle? no yes yes read q7 ~ q0 (note 1) (note 1,2)
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 38/46 figure 21. data polling timings (during embedded algorithms) notes : va = valid address. figure shows first status cycle a fter command sequence, last status read cycle, and array data read cycle. we address ce oe t acc dq7 ry/by t ce va va t rc t oe t oeh t ch t df t oh complement complement true vaild data high-z status data status data true vaild data high-z dq0~dq6 t busy
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 39/46 figure 22. toggle bit timing wavefo rms (during embedded algorithms) notes : va = valid address; not required for dq6. figure shows first status cycle after command sequence, last status read cycle, and array data read cycle. address ce oe we t acc dq6/dq2 ry/by t ce va va t rc t oe t oeh t ch t df t oh vaild status t busy va vaild status va high-z (fi rst read) (second read) vaild data (stops toggling) vaild data
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 40/46 10.3 hardware reset operation table 13. ac characteristics (for 40-pin tsop package type) symbol description all speed options unit t ready1 eset r pin low (during embedded algorithms) to read or write (see note) max 20 us t ready2 eset r pin low (not during embedded algorithms) to read or write (see note) max 500 ns t rp eset r pulse width (during embedded algorithms) min 500 ns t rh eset r high time before read(see note) min 50 ns t rb ry/ by recovery time(to ce , oe go low) min 0 ns notes : not 100% tested figure 23. rese t timing waveform (for 40-pin tsop package type) ry/by ce, oe reset ry/by ce, oe reset t rp t ready2 t rh t rp t rb t ready1 reset timing not during automatic algorithms reset timing during automatic algorithms
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 41/46 10.4 temporary sector unprotect operation table 14. temporary sector unprotect symbol description all speed options unit t vidr v id rise and fall time (see note) min 500 ns t rsp eset r setup time for temporary sector unprotect min 4 us notes: not 100% tested figure 24. temporary sector unprotect timing diagram figure 25. q6 vs q2 for erase and erase suspend operations notes : the system can use oe or ce to toggle dq2 / dq6, dq2 t oggles only when read at an address within an erase-suspended. we ry/by ce reset t vidr t rsp 0 or v cc program or erase command sequence t vidr 0 or v cc we dq6 dq2 enter embedded erasing erase suspend enter erase suspend program erase suspend program erase suspend read erase resume erase erase complete
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 42/46 figure 26. temporary sector unprotect algorithm notes : 1. all protected status are temporary unprotect. v id = 11.5v~12.5v 2. all previously protected sectors are protected again. start reset = v id (note 1) reset = v ih program erase or program operation temporary sector unprotect completed (note 2) operation completed
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 43/46 figure 27. id code read timing waveform add a2~a8 a10~a18 ce we oe v ih v ih v ih v il v il v il v ih v il v ih v il v ih v il v ih v il vcc 3v t acc t ce t acc v id t oe add a9 add a0 a1 data dq0~dq7 v ih v il t oh t oh t df data out b5h/b6h data out c2h
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 44/46 11. erase and programming performance table 15. erase and programming performance (note.1) limits parameter min. typ.(2) max.(3) unit sector erase time 0.7 15 sec chip erase time 11 sec byte programming time 9 300 us chip programming time 4.5 13.5 sec erase/program cycles 100,000 cycles notes: 1.not 100% tested, excludes external system level over head. 2.typical values measured at 25c, 3v. 3.maximum values measured at 25c, 2.7v.
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 45/46 12. package dimension 32-pin plcc symbol dimension in mm dimension in inch min norm max min norm max a 3.18 ------- 3.55 0.125 ------- 0.140 a 1 1.53 ------- 2.41 0.060 ------- 0.095 a 2 2.79 ref 0.110 ref b 0.33 ------- 0.54 0.013 ------- 0.021 b2 0.66 ------- 0.82 0.026 ------- 0.032 c 0.20 ------- 0.36 0.008 ------- 0.014 e 1.27 bsc 0.050 bsc 0 o ------- 10 o 0 o ------- 10 o e 14.86 14.99 15.11 0.585 0.590 0.595 e 1 13.90 13.97 14.04 0.547 0.550 0.553 e 2 6.05 ------- 6.93 0.238 ------- 0.273 e 3 10.16 bsc 0.400 bsc d 12.32 12.45 12.57 0.485 0.490 0.495 d 1 11.36 11.43 11.50 0.447 0.450 0.453 d 2 4.78 ------- 5.66 0.188 ------- 0.223 d 3 7.62 bsc 0.300 bsc d d 1 e 1 e a 0.020" min seating plane 0.004 2 d -c- e 2 -c- 1 a 14 20 13 5 4 21 32 1 30 29 d 2 o e 2 e b b 2 c d 3 e 3 a 2
efst preliminary F49L004UA / f49l004ba elite flash storage technology inc. publication date : aug. 2003 revision: 0.2 46/46 important notice all rights reserved. no part of this document may be rep roduced or duplicated in any form or by any means without the prior permission of efst. the contents contained in this doc ument are believed to be accurate at the time of publication. efst assu mes no responsibility for any error in this document, and reserves t he right to change the products or specification in this document without notice. the information contai ned herein is presented only as a guide or examples for the application of ou r products. no responsibility is assumed by efst for any infringement of patents, copyrights, or other intellectual property rights of third par ties which may result from its use. no license, either express , impli ed or otherwise, is granted under any patents, copyrights or other intellectual pr operty rights of efst or others. any semiconductor devices may have in herently a certain rate of failure. to minimize risks associated with customer's application, adequate design and operating safe guards against inju ry, damage, or loss from such failure, should be provid ed by the customer when making application designs. efst 's products are not au thorized for use in critical applications such as, but not limited to, life supp ort devices or syst em, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. if products described here are to be used for such kinds of application, purchas er must do its ow n quality assurance testing appropriate to such applications.

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